/*
 * Copyright     :  Copyright (C) 2021, Huawei Technologies Co. Ltd.
 * File name     :  hipciec50_ap_engine_reg_reg_offset_field.h
 * Project line  :  
 * Department    :  CAD Development Department
 * Author        :  kuangxiaobo/262329
 * Version       :  1.0
 * Date          :  
 * Description   :  PCIE Controller 5.0  Version 200
 * Others        :  Generated automatically by nManager V5.1 
 * History       :  kuangxiaobo/262329 2021/10/23 17:24:58 Create file
 */

#ifndef __HIPCIEC50_AP_ENGINE_REG_REG_OFFSET_FIELD_H__
#define __HIPCIEC50_AP_ENGINE_REG_REG_OFFSET_FIELD_H__

#define HIPCIEC50_AP_ENGINE_REG_CFG_RAM_ECC_INT_SEVERITY_LEN    4
#define HIPCIEC50_AP_ENGINE_REG_CFG_RAM_ECC_INT_SEVERITY_OFFSET 6

#define HIPCIEC50_AP_ENGINE_REG_CFG_LAST_EXT_LAST_MODE_LEN    1
#define HIPCIEC50_AP_ENGINE_REG_CFG_LAST_EXT_LAST_MODE_OFFSET 1
#define HIPCIEC50_AP_ENGINE_REG_DMA_SMMU_BYPASS_CFG_LEN       1
#define HIPCIEC50_AP_ENGINE_REG_DMA_SMMU_BYPASS_CFG_OFFSET    0

#define HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_DMA_MEM_DAW_0_H_LEN    16
#define HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_DMA_MEM_DAW_0_H_OFFSET 0

#define HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_DMA_MEM_DAT_0_L_LEN    32
#define HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_DMA_MEM_DAT_0_L_OFFSET 0

#define HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_DMA_MEM_DAW_1_H_LEN    16
#define HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_DMA_MEM_DAW_1_H_OFFSET 0

#define HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_DMA_MEM_DAT_1_L_LEN    32
#define HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_DMA_MEM_DAT_1_L_OFFSET 0

#define HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_DMA_MEM_DAW_2_H_LEN    16
#define HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_DMA_MEM_DAW_2_H_OFFSET 0

#define HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_DMA_MEM_DAT_2_L_LEN    32
#define HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_DMA_MEM_DAT_2_L_OFFSET 0

#define HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_DMA_MEM_DAW_3_H_LEN    16
#define HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_DMA_MEM_DAW_3_H_OFFSET 0

#define HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_DMA_MEM_DAT_3_L_LEN    32
#define HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_DMA_MEM_DAT_3_L_OFFSET 0

#define HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_DMA_MEM_DAW_4_H_LEN    16
#define HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_DMA_MEM_DAW_4_H_OFFSET 0

#define HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_DMA_MEM_DAT_4_L_LEN    32
#define HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_DMA_MEM_DAT_4_L_OFFSET 0

#define HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_DMA_MEM_DAW_5_H_LEN    16
#define HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_DMA_MEM_DAW_5_H_OFFSET 0

#define HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_DMA_MEM_DAT_5_L_LEN    32
#define HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_DMA_MEM_DAT_5_L_OFFSET 0

#define HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_DMA_MEM_DAW_6_H_LEN    16
#define HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_DMA_MEM_DAW_6_H_OFFSET 0

#define HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_DMA_MEM_DAT_6_L_LEN    32
#define HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_DMA_MEM_DAT_6_L_OFFSET 0

#define HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_MCTP_MEM_DAW_0_LL_LEN    32
#define HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_MCTP_MEM_DAW_0_LL_OFFSET 0

#define HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_MCTP_MEM_DAW_0_LH_LEN    16
#define HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_MCTP_MEM_DAW_0_LH_OFFSET 0

#define HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_MCTP_MEM_DAW_0_HL_LEN    32
#define HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_MCTP_MEM_DAW_0_HL_OFFSET 0

#define HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_MCTP_MEM_DAW_0_HH_LEN    16
#define HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_MCTP_MEM_DAW_0_HH_OFFSET 0

#define HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_MCTP_MEM_DAW_1_LL_LEN    32
#define HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_MCTP_MEM_DAW_1_LL_OFFSET 0

#define HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_MCTP_MEM_DAW_1_LH_LEN    16
#define HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_MCTP_MEM_DAW_1_LH_OFFSET 0

#define HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_MCTP_MEM_DAW_1_HL_LEN    32
#define HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_MCTP_MEM_DAW_1_HL_OFFSET 0

#define HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_MCTP_MEM_DAW_1_HH_LEN    16
#define HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_MCTP_MEM_DAW_1_HH_OFFSET 0

#define HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_IEP_MEM_DAW_0_H_LEN    16
#define HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_IEP_MEM_DAW_0_H_OFFSET 0

#define HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_IEP_MEM_DAT_0_L_LEN    32
#define HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_IEP_MEM_DAT_0_L_OFFSET 0

#define HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_IEP_MEM_DAW_1_H_LEN    16
#define HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_IEP_MEM_DAW_1_H_OFFSET 0

#define HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_IEP_MEM_DAT_1_L_LEN    32
#define HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_IEP_MEM_DAT_1_L_OFFSET 0

#define HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_DMA_SNPATTR_3_LEN    1
#define HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_DMA_SNPATTR_3_OFFSET 28
#define HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_DMA_CACHE_3_LEN      4
#define HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_DMA_CACHE_3_OFFSET   24
#define HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_DMA_SNPATTR_2_LEN    1
#define HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_DMA_SNPATTR_2_OFFSET 20
#define HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_DMA_CACHE_2_LEN      4
#define HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_DMA_CACHE_2_OFFSET   16
#define HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_DMA_SNPATTR_1_LEN    1
#define HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_DMA_SNPATTR_1_OFFSET 12
#define HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_DMA_CACHE_1_LEN      4
#define HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_DMA_CACHE_1_OFFSET   8
#define HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_DMA_SNPATTR_0_LEN    1
#define HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_DMA_SNPATTR_0_OFFSET 4
#define HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_DMA_CACHE_0_LEN      4
#define HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_DMA_CACHE_0_OFFSET   0

#define HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_DMA_SNPATTR_7_LEN    1
#define HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_DMA_SNPATTR_7_OFFSET 28
#define HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_DMA_CACHE_7_LEN      4
#define HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_DMA_CACHE_7_OFFSET   24
#define HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_DMA_SNPATTR_6_LEN    1
#define HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_DMA_SNPATTR_6_OFFSET 20
#define HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_DMA_CACHE_6_LEN      4
#define HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_DMA_CACHE_6_OFFSET   16
#define HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_DMA_SNPATTR_5_LEN    1
#define HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_DMA_SNPATTR_5_OFFSET 12
#define HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_DMA_CACHE_5_LEN      4
#define HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_DMA_CACHE_5_OFFSET   8
#define HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_DMA_SNPATTR_4_LEN    1
#define HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_DMA_SNPATTR_4_OFFSET 4
#define HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_DMA_CACHE_4_LEN      4
#define HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_DMA_CACHE_4_OFFSET   0

#define HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_IEP_CFG_SNPATTR_LEN    1
#define HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_IEP_CFG_SNPATTR_OFFSET 4
#define HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_IEP_CFG_CACHE_LEN      4
#define HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_IEP_CFG_CACHE_OFFSET   0

#define HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_RCP_SNPATTR_LEN    1
#define HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_RCP_SNPATTR_OFFSET 4
#define HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_RCP_CACHE_LEN      4
#define HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_RCP_CACHE_OFFSET   0

#define HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_NVME_SNPATTR_LEN    1
#define HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_NVME_SNPATTR_OFFSET 4
#define HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_NVME_CACHE_LEN      4
#define HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_NVME_CACHE_OFFSET   0

#define HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_MCTP_SNPATTR0_LEN    1
#define HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_MCTP_SNPATTR0_OFFSET 4
#define HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_MCTP_CACHE0_LEN      4
#define HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_MCTP_CACHE0_OFFSET   0

#define HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_MCTP_SNPATTR1_LEN    1
#define HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_MCTP_SNPATTR1_OFFSET 4
#define HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_MCTP_CACHE1_LEN      4
#define HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_MCTP_CACHE1_OFFSET   0

#define HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_MCTP_SNPATTR2_LEN    1
#define HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_MCTP_SNPATTR2_OFFSET 4
#define HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_MCTP_CACHE2_LEN      4
#define HIPCIEC50_AP_ENGINE_REG_RBA_CTRL_MCTP_CACHE2_OFFSET   0

#define HIPCIEC50_AP_ENGINE_REG_RBA_WEIGHT_CFG_LEN    30
#define HIPCIEC50_AP_ENGINE_REG_RBA_WEIGHT_CFG_OFFSET 0

#define HIPCIEC50_AP_ENGINE_REG_RBA2IB_ACTIVE_CFG_LEN         1
#define HIPCIEC50_AP_ENGINE_REG_RBA2IB_ACTIVE_CFG_OFFSET      5
#define HIPCIEC50_AP_ENGINE_REG_RBA2MCTP_NP_ACTIVE_CFG_LEN    1
#define HIPCIEC50_AP_ENGINE_REG_RBA2MCTP_NP_ACTIVE_CFG_OFFSET 4
#define HIPCIEC50_AP_ENGINE_REG_RBA2IEP_ACTIVE_CFG_LEN        1
#define HIPCIEC50_AP_ENGINE_REG_RBA2IEP_ACTIVE_CFG_OFFSET     3
#define HIPCIEC50_AP_ENGINE_REG_RBA2NVME_ACTIVE_CFG_LEN       1
#define HIPCIEC50_AP_ENGINE_REG_RBA2NVME_ACTIVE_CFG_OFFSET    2
#define HIPCIEC50_AP_ENGINE_REG_RBA2RCP_ACTIVE_CFG_LEN        1
#define HIPCIEC50_AP_ENGINE_REG_RBA2RCP_ACTIVE_CFG_OFFSET     1
#define HIPCIEC50_AP_ENGINE_REG_RBA2MCTP_ACTIVE_CFG_LEN       1
#define HIPCIEC50_AP_ENGINE_REG_RBA2MCTP_ACTIVE_CFG_OFFSET    0

#define HIPCIEC50_AP_ENGINE_REG_DEEP_WR_EN_LEN     1
#define HIPCIEC50_AP_ENGINE_REG_DEEP_WR_EN_OFFSET  3
#define HIPCIEC50_AP_ENGINE_REG_RCP_END_CFG_LEN    3
#define HIPCIEC50_AP_ENGINE_REG_RCP_END_CFG_OFFSET 0

#define HIPCIEC50_AP_ENGINE_REG_NVME_END_CFG_LEN    3
#define HIPCIEC50_AP_ENGINE_REG_NVME_END_CFG_OFFSET 0

#define HIPCIEC50_AP_ENGINE_REG_MCTP_PROTECT_LEN    1
#define HIPCIEC50_AP_ENGINE_REG_MCTP_PROTECT_OFFSET 3
#define HIPCIEC50_AP_ENGINE_REG_IEP_BYPASS_LEN      1
#define HIPCIEC50_AP_ENGINE_REG_IEP_BYPASS_OFFSET   2
#define HIPCIEC50_AP_ENGINE_REG_IEP_SO_CFG_LEN      1
#define HIPCIEC50_AP_ENGINE_REG_IEP_SO_CFG_OFFSET   1
#define HIPCIEC50_AP_ENGINE_REG_ORDER_CFG_LEN       1
#define HIPCIEC50_AP_ENGINE_REG_ORDER_CFG_OFFSET    0

#define HIPCIEC50_AP_ENGINE_REG_RCP_NVME_ICG_EN_LEN    1
#define HIPCIEC50_AP_ENGINE_REG_RCP_NVME_ICG_EN_OFFSET 2
#define HIPCIEC50_AP_ENGINE_REG_IEP_ICG_EN_LEN         1
#define HIPCIEC50_AP_ENGINE_REG_IEP_ICG_EN_OFFSET      1
#define HIPCIEC50_AP_ENGINE_REG_MCTP_ICG_EN_LEN        1
#define HIPCIEC50_AP_ENGINE_REG_MCTP_ICG_EN_OFFSET     0

#define HIPCIEC50_AP_ENGINE_REG_AP_ENG_SEC_CTRL_LEN    1
#define HIPCIEC50_AP_ENGINE_REG_AP_ENG_SEC_CTRL_OFFSET 0

#define HIPCIEC50_AP_ENGINE_REG_DFX_RBA_CNT_DATA_REQ_LEN    16
#define HIPCIEC50_AP_ENGINE_REG_DFX_RBA_CNT_DATA_REQ_OFFSET 16
#define HIPCIEC50_AP_ENGINE_REG_DFX_RBA_CNT_HEAD_LEN        16
#define HIPCIEC50_AP_ENGINE_REG_DFX_RBA_CNT_HEAD_OFFSET     0

#define HIPCIEC50_AP_ENGINE_REG_DFX_RBA_CNT_ERR_HEAD_LEN    16
#define HIPCIEC50_AP_ENGINE_REG_DFX_RBA_CNT_ERR_HEAD_OFFSET 0

#define HIPCIEC50_AP_ENGINE_REG_DFX_RBA_BUFFER_USED_RD_LEN    8
#define HIPCIEC50_AP_ENGINE_REG_DFX_RBA_BUFFER_USED_RD_OFFSET 8
#define HIPCIEC50_AP_ENGINE_REG_DFX_RBA_BUFFER_USED_WR_LEN    8
#define HIPCIEC50_AP_ENGINE_REG_DFX_RBA_BUFFER_USED_WR_OFFSET 0

#define HIPCIEC50_AP_ENGINE_REG_DFX_RBA_BUFFER_USED_IEP_LEN     4
#define HIPCIEC50_AP_ENGINE_REG_DFX_RBA_BUFFER_USED_IEP_OFFSET  4
#define HIPCIEC50_AP_ENGINE_REG_DFX_RBA_BUFFER_USED_NVME_LEN    2
#define HIPCIEC50_AP_ENGINE_REG_DFX_RBA_BUFFER_USED_NVME_OFFSET 2
#define HIPCIEC50_AP_ENGINE_REG_DFX_RBA_BUFFER_USED_RCP_LEN     2
#define HIPCIEC50_AP_ENGINE_REG_DFX_RBA_BUFFER_USED_RCP_OFFSET  0

#define HIPCIEC50_AP_ENGINE_REG_DFX_RBA_ARBITER_EN_LEN    1
#define HIPCIEC50_AP_ENGINE_REG_DFX_RBA_ARBITER_EN_OFFSET 0

#define HIPCIEC50_AP_ENGINE_REG_DFX_RCP_NVME_IDLE_LEN    1
#define HIPCIEC50_AP_ENGINE_REG_DFX_RCP_NVME_IDLE_OFFSET 3
#define HIPCIEC50_AP_ENGINE_REG_DFX_IEP_IDLE_LEN         1
#define HIPCIEC50_AP_ENGINE_REG_DFX_IEP_IDLE_OFFSET      2
#define HIPCIEC50_AP_ENGINE_REG_DFX_MCTP_IDLE_LEN        1
#define HIPCIEC50_AP_ENGINE_REG_DFX_MCTP_IDLE_OFFSET     1
#define HIPCIEC50_AP_ENGINE_REG_DFX_RBA_IDLE_LEN         1
#define HIPCIEC50_AP_ENGINE_REG_DFX_RBA_IDLE_OFFSET      0

#define HIPCIEC50_AP_ENGINE_REG_CFG_RAM_ECC_ERR_INJECT_WR_LEN    3
#define HIPCIEC50_AP_ENGINE_REG_CFG_RAM_ECC_ERR_INJECT_WR_OFFSET 3
#define HIPCIEC50_AP_ENGINE_REG_CFG_RAM_ECC_ERR_INJECT_RD_LEN    3
#define HIPCIEC50_AP_ENGINE_REG_CFG_RAM_ECC_ERR_INJECT_RD_OFFSET 0

#define HIPCIEC50_AP_ENGINE_REG_RAM_ECC_2BIT_ERR_ADDR_LEN    16
#define HIPCIEC50_AP_ENGINE_REG_RAM_ECC_2BIT_ERR_ADDR_OFFSET 16
#define HIPCIEC50_AP_ENGINE_REG_RAM_ECC_1BIT_ERR_ADDR_LEN    16
#define HIPCIEC50_AP_ENGINE_REG_RAM_ECC_1BIT_ERR_ADDR_OFFSET 0

#define HIPCIEC50_AP_ENGINE_REG_RAM_ECC_1BIT_CNT_WR_LEN    5
#define HIPCIEC50_AP_ENGINE_REG_RAM_ECC_1BIT_CNT_WR_OFFSET 5
#define HIPCIEC50_AP_ENGINE_REG_RAM_ECC_1BIT_CNT_RD_LEN    5
#define HIPCIEC50_AP_ENGINE_REG_RAM_ECC_1BIT_CNT_RD_OFFSET 0

#define HIPCIEC50_AP_ENGINE_REG_RAM_ECC_2BIT_CNT_WR_LEN    5
#define HIPCIEC50_AP_ENGINE_REG_RAM_ECC_2BIT_CNT_WR_OFFSET 5
#define HIPCIEC50_AP_ENGINE_REG_RAM_ECC_2BIT_CNT_RD_LEN    5
#define HIPCIEC50_AP_ENGINE_REG_RAM_ECC_2BIT_CNT_RD_OFFSET 0

#define HIPCIEC50_AP_ENGINE_REG_RBA_INTECC_RO_CE_WR_LEN    1
#define HIPCIEC50_AP_ENGINE_REG_RBA_INTECC_RO_CE_WR_OFFSET 1
#define HIPCIEC50_AP_ENGINE_REG_RBA_INTECC_RO_CE_RD_LEN    1
#define HIPCIEC50_AP_ENGINE_REG_RBA_INTECC_RO_CE_RD_OFFSET 0

#define HIPCIEC50_AP_ENGINE_REG_RBA_INTECC_RO_NFE_WR_LEN    2
#define HIPCIEC50_AP_ENGINE_REG_RBA_INTECC_RO_NFE_WR_OFFSET 2
#define HIPCIEC50_AP_ENGINE_REG_RBA_INTECC_RO_NFE_RD_LEN    2
#define HIPCIEC50_AP_ENGINE_REG_RBA_INTECC_RO_NFE_RD_OFFSET 0

#define HIPCIEC50_AP_ENGINE_REG_RBA_INTECC_RO_FE_WR_LEN    1
#define HIPCIEC50_AP_ENGINE_REG_RBA_INTECC_RO_FE_WR_OFFSET 1
#define HIPCIEC50_AP_ENGINE_REG_RBA_INTECC_RO_FE_RD_LEN    1
#define HIPCIEC50_AP_ENGINE_REG_RBA_INTECC_RO_FE_RD_OFFSET 0

#define HIPCIEC50_AP_ENGINE_REG_CFG_RAM_ECC_INT_SET_LEN    4
#define HIPCIEC50_AP_ENGINE_REG_CFG_RAM_ECC_INT_SET_OFFSET 0

#define HIPCIEC50_AP_ENGINE_REG_CFG_RAM_ECC_INT_MASK_LEN    4
#define HIPCIEC50_AP_ENGINE_REG_CFG_RAM_ECC_INT_MASK_OFFSET 0

#define HIPCIEC50_AP_ENGINE_REG_RBA_RAM_ECC_INT_STATUS_LEN    4
#define HIPCIEC50_AP_ENGINE_REG_RBA_RAM_ECC_INT_STATUS_OFFSET 0

#define HIPCIEC50_AP_ENGINE_REG_RBA_RAM_ECC_INT_RO_LEN    4
#define HIPCIEC50_AP_ENGINE_REG_RBA_RAM_ECC_INT_RO_OFFSET 0

#define HIPCIEC50_AP_ENGINE_REG_RAM_ECC_2BIT_ERR_ADDR_WR_LEN    16
#define HIPCIEC50_AP_ENGINE_REG_RAM_ECC_2BIT_ERR_ADDR_WR_OFFSET 16
#define HIPCIEC50_AP_ENGINE_REG_RAM_ECC_1BIT_ERR_ADDR_WR_LEN    16
#define HIPCIEC50_AP_ENGINE_REG_RAM_ECC_1BIT_ERR_ADDR_WR_OFFSET 0

#define HIPCIEC50_AP_ENGINE_REG_IEP_PAB_PAGE_FAULT_RSLT_IDX_LEN    10
#define HIPCIEC50_AP_ENGINE_REG_IEP_PAB_PAGE_FAULT_RSLT_IDX_OFFSET 0

#define HIPCIEC50_AP_ENGINE_REG_IEP_PAB_PAGE_FAULT_RSLT_ADDR_LOW_LEN    32
#define HIPCIEC50_AP_ENGINE_REG_IEP_PAB_PAGE_FAULT_RSLT_ADDR_LOW_OFFSET 0

#define HIPCIEC50_AP_ENGINE_REG_IEP_PAB_PAGE_FAULT_RSLT_ADDR_HIGH_LEN    32
#define HIPCIEC50_AP_ENGINE_REG_IEP_PAB_PAGE_FAULT_RSLT_ADDR_HIGH_OFFSET 0

#endif // __HIPCIEC50_AP_ENGINE_REG_REG_OFFSET_FIELD_H__
